soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• Design and Implementation of Multi-channel Phone-billing-system Based upon NIOS Soft-core CPU
  基于NIOS软核CPU技术的多路电话计费系统的设计与实现
• To solute the problem, the idea of kernel hardware design has been put forward. System architecture is divided into soft-core and hardcore. Hardcore will manage application tasks as a coprocessor to improve the real time of system.
  针对实时性问题，提出将内核硬件化设计的思想，将系统的体系结构划分为软核和硬核，硬核作为协处理器管理应用任务，提高系统的实时性，使系统的性能得到明显的提高。
• The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors.
  网络处理器芯片原型采用NIOSii软核处理器在FPGA上实现，提高了网络处理器的可编程能力。
• The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
  通过使用SOPC技术，在FPGA内部构建了NIOSⅡ软核处理器，并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统，从而实现了对系统任务的调度。
• It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
  它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。
• Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system.
  采用FPGA作为控制芯片，在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
• First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
  先对灰度量化算法进行了分析和仿真比较，然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
• Research and Design of Soft-core IP for AVS Inter Decoder
  AVS帧间解码IP软核的研究与设计
• A 40Gb/ s switch IP soft-core with self-dependence intellectual property was realized.
  形成了具有自主知识产权的40Gb/s交换IP软核。